1. Field of the Invention
This invention relates to the microprogrammed control units used in data processing systems.
2. Description of the Prior Art
It is well known that modern data processing systems include a control unit which allows the system to interpret and execute instructions by means of suitable microprograms, the several program instructions forming the work program or programs assigned to the system. In other words, each instruction to be executed recalls a microprogram formed by several microinstructions and each microinstruction is executed during a machine cycle. Modern data processing systems are described, for example, in U.S. Pat. Nos. 3,812,464; 3,872,447; 3,956,738; 3,991,404; 3,949,372; and in several other patents.
The interpretation and the execution of each instruction generally require several machine cycles and the execution of several microinstructions of a microprogram. It is well known that the microinstructions are generally stored in a microprogram read only memory from which they are read out, one by one at each machine cycle, and decoded in a set of microcommands. These microcommands control the elementary operations of the processor during each machine cycle.
The expressive power of a microinstruction is limited by its parallelism, that is, by the number of bits composing it. The more bits in parallel, the greater the number of independent microcommands generated during the same machine cycle. Processor architecture and cost saving reasons generally lead to the use of a reduced microinstruction parallelism. Such parallelism is generally lower than that of which would be required in order to develop, at the same time, all the microcommands that the process or can execute during one machine cycle. Therefore, many operations which could be executed at the same time must be executed during subsequent machine cycles.
It is also well known, for example, that the microinstructions are generally classified in operative microinstructions and jump microinstructions. In an operative microinstruction, the constituting bits express in coded form some operative microcommands which actually control operations of addition, subtraction, comparison, transfer from register to register, etc. For such microinstructions, the read out of the subsequent microinstruction sequentially occurs by incrementing by one unit the address of the previous microinstruction. In fact, in the format of the operative microinstructions, there are not enough bits to specify the address of the next microinstruction in either absolute or relative terms; nor are there enough bits to provide, directly or indirectly, the address of a register within which the effective address of the subsequent microinstruction is stored.
By contrast, in a jump microinstruction the constituting bits express in coded form some microcommands which command some operations of non-sequential addressing of the next microinstruction and provide in an absolute or a relative way, directly or indirectly, the address of the subsequent microinstruction. In the case of a conditioned jump microinstruction, the non-sequential addressing of the next microinstruction is indicated by the occurrence of a determined condition, directly or indirectly shown by a field of the same microinstruction.
In the format of such microinstructions, bit fields of sizes suitable to carry out different operations (that is, logical/arithmetical operations or transfer operations) do not remain available to carry out conditioned jumps to several different and independent addresses owing to the occurrence of several different conditions. In fact, this last feature would require that the microinstruction have the capability of providing several addresses and several jump conditions at the same time.